Parallel processing in APLAC : Part A, DC and transient analyses

Parallel processing in APLAC : Part A, DC and transient analyses

datePublished

• 2003

description

• kuvitettu

identifier

• propertyID: FI-FENNI value: 739470
• propertyID: FI-MELINDA value: 000273724
• propertyID: skl value: fx739470

isbn

• 9512265125

isPartOf

• Circuit Theory Lab. rep. ser
• Fennica

name

• Parallel processing in APLAC : Part A, DC and transient analyses

numberOfPages

• ii, 16, [2] s.

P60048

• <http://rdaregistry.info/termList/RDACarrierType/1049>

P60050

• <http://rdaregistry.info/termList/RDAMediaType/1007>

publication

• location: Espoo organizer: Teknillinen korkeakoulu

publisher

• Teknillinen korkeakoulu