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A VLSI array processor architecture for emulating resistive network filtering
URI:
http://urn.fi/URN:NBN:fi:bib:me:W00048002800
author
Kananen, Asko
contributor
Teknillinen korkeakoulu. Piiritekniikan laboratorio
inLanguage
en
isPartOf
Fennica
name
A VLSI array processor architecture for emulating resistive network filtering
P60049
<http://rdaregistry.info/termList/RDAContentType/1020>
Instances
-
2007 : Helsinki University of Technology, Department of Electrical and Communications Engineering
A VLSI array processor architecture for emulating resistive network filtering
URI:
http://urn.fi/URN:NBN:fi:bib:me:I00048002801
description
Julkaistu myös verkkoaineistona
isPartOf
Fennica
TKK dissertations
name
A VLSI array processor architecture for emulating resistive network filtering
View this in Finna
A VLSI array processor architecture for emulating resistive network filtering
URI:
http://urn.fi/URN:NBN:fi:bib:me:I00048002800
datePublished
2007
description
kuvitettu
identifier
propertyID:
FI-FENNI
value:
859262
propertyID:
FI-MELINDA
value:
000480028
propertyID:
skl
value:
fx859262
isbn
9789512286225
isPartOf
Fennica
TKK dissertations
name
A VLSI array processor architecture for emulating resistive network filtering
numberOfPages
xiii, 124, [1] sivu
P60048
<http://rdaregistry.info/termList/RDACarrierType/1049>
P60050
<http://rdaregistry.info/termList/RDAMediaType/1007>
publication
location:
Espoo
organizer:
Helsinki University of Technology, Department of Electrical and Communications Engineering
publisher
Helsinki University of Technology, Department of Electrical and Communications Engineering
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