Implementation of instruction-level and thread-level parallelism in computers

Implementation of instruction-level and thread-level parallelism in computers

datePublished

• 1997

description

• kuvitettu

identifier

• propertyID: FI-FENNI value: 572844
• propertyID: FI-MELINDA value: 000154469
• propertyID: skl value: fx572844

isbn

• 9517085575

isPartOf

• Dissertations
• Fennica

name

• Implementation of instruction-level and thread-level parallelism in computers

numberOfPages

• xii, 121 s.

P60048

• <http://rdaregistry.info/termList/RDACarrierType/1049>

P60050

• <http://rdaregistry.info/termList/RDAMediaType/1007>

publication

• location: Joensuu organizer: Joensuun yliopisto

publisher

• Joensuun yliopisto