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Design of systolic algorithms and architectures for digital signal processing
URI:
http://urn.fi/URN:NBN:fi:bib:me:W00009335100
author
Wang, Ling
contributor
Teknillinen korkeakoulu. Signaalinkäsittely- ja tietokonetekniikan laboratorio
inLanguage
en
isPartOf
Fennica
name
Design of systolic algorithms and architectures for digital signal processing
P60049
<http://rdaregistry.info/termList/RDAContentType/1020>
Instances
1991 : Teknillinen korkeakoulu
View this in Finna
Design of systolic algorithms and architectures for digital signal processing
URI:
http://urn.fi/URN:NBN:fi:bib:me:I00009335100
datePublished
1991
description
kuvitettu
identifier
propertyID:
FI-FENNI
value:
360834
propertyID:
FI-MELINDA
value:
000093351
propertyID:
skl
value:
fx360834
isbn
9512218550
isPartOf
Fennica
Report
name
Design of systolic algorithms and architectures for digital signal processing
numberOfPages
xi, 31, [45] s.
P60048
<http://rdaregistry.info/termList/RDACarrierType/1049>
P60050
<http://rdaregistry.info/termList/RDAMediaType/1007>
publication
location:
Otaniemi
organizer:
Teknillinen korkeakoulu
publisher
Teknillinen korkeakoulu
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