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    schema:name "The minimal pipeline architecture" .

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    schema:name "Implementation of instruction-level and thread-level parallelism in computers" .

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    schema:name "MTAC : a multithreated VLIW architecture for PRAM simulation" .

<http://urn.fi/URN:NBN:fi:bib:me:W00043382500> schema:author <http://urn.fi/URN:NBN:fi:au:pn:000085621> ;
    schema:name "Are multiport memories physically feasible?" .

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    schema:name "Primitives of sequential and parallel computation" .

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    schema:name "Architectural differences of efficient sequential and parallel computers" .

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    schema:name "Memory module structures for shared memory simulation" .

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    schema:name "Context-based compression of binary images in parallel" .

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    schema:name "Efficient two-level mesh based simulation of PRAMS" .

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    schema:name "Forsell, Martti" .