Modeling and analysis of noise and interconnects for on-chip communication link design

author
inLanguage
  • en
isPartOf
name
  • Modeling and analysis of noise and interconnects for on-chip communication link design
P60049

Instances

Modeling and analysis of noise and interconnects for on-chip communication link design

description
  • Julkaistu myös verkkoaineistona ISBN 978-951-29-4767-6 (PDF)
isPartOf
name
  • Modeling and analysis of noise and interconnects for on-chip communication link design

Modeling and analysis of noise and interconnects for on-chip communication link design

bookFormat
isPartOf
name
  • Modeling and analysis of noise and interconnects for on-chip communication link design
url

Modeling and analysis of noise and interconnects for on-chip communication link design

bookFormat
isPartOf
name
  • Modeling and analysis of noise and interconnects for on-chip communication link design
url

Modeling and analysis of noise and interconnects for on-chip communication link design

datePublished
  • 2011
description
  • kuvitettu
identifier
  • propertyID: FI-FENNI value: 992599
  • propertyID: FI-MELINDA value: 005959241
  • propertyID: skl value: fx992599
isbn
  • 9789512947669
isPartOf
name
  • Modeling and analysis of noise and interconnects for on-chip communication link design
numberOfPages
  • 119 s.
P60048
P60050
publication
  • location: Turku organizer: Turun yliopisto
publisher

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